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July 2001
CT RODU D UC T LETE P TITUTE PRO IL BSO O SUBS -888-INTERS SIBLE 1 A POS pplications ersil.com FO R ral A ntapp@int nt call Ce mail: ce or e
ICM7217
4-Digit LED Display, Programmable Up/Down Counter
Features [ /Title (ICM7 217) /Subject (4igit ED isplay, Programmable Up/Do wn Counte r) /Autho r () /Keywords (Intersil Corporation, Semiconductor, Programmable UpDown Counte r, Common Anode, LED, Com* Four Decade, Presettable Up-Down Counter with Parallel Zero Detect * Settable Register with Contents Continuously Compared to Counter * Directly Drives Multiplexed 7 Segment Common Anode or Common Cathode LED Displays * On-Board Multiplex Scan Oscillator * Schmitt Trigger On Count Input * TTL Compatible BCD I/O Port, Carry/Borrow, Equal, and Zero Outputs * Display Blank Control for Lower Power Operation; Quiescent Power Dissipation <5mW * All Terminals Fully Protected Against Static Discharge * Single 5V Supply Operation
Description
The ICM7217 is a four digit, presettable up/down counter with an onboard presettable register continuously compared to the counter. The ICM7217 is intended for use in hard-wired applications where thumbwheel switches are used for loading data, and simple SPDT switches are used for chip control. This circuit provides multiplexed 7 segment LED display outputs, with common anode or common cathode configurations available. Digit and segment drivers are provided to directly drive displays of up to 0.8 inch character height (common anode) at a 25% duty cycle. The frequency of the onboard multiplex oscillator may be controlled with a single capacitor, or the oscillator may be allowed to free run. Leading zeros can be blanked. The data appearing at the 7 segment and BCD outputs is latched; the content of the counter is transferred into the latches under external control by means of the Store pin. The ICM7217 (common anode) and ICM7217A (common cathode) versions are decade counters, providing a maximum count of 9999, while the ICM7217B (common anode) and ICM7217C (common cathode) are intended for timing purposes, providing a maximum count of 5959. This circuit provides 3 main outputs; a CARRY/BORROW output, which allows for direct cascading of counters, a ZERO output, which indicates when the count is zero, and an EQUAL output, which indicates when the count is equal to the value contained in the register. Data is multiplexed to and from the device by means of a three-state BCD I/O port. The CARRY/BORROW, EQUAL, ZERO outputs, and the BCD port will each drive one standard TTL load. To permit operation in noisy environments and to prevent multiple triggering with slowly changing inputs, the count input is provided with a Schmitt trigger. Input frequency is guaranteed to 2MHz, although the device will typically run with fIN as high as 5MHz. Counting and comparing (EQUAL output) will typically run 750kHz maximum.
Part Number Information
PART NUMBER ICM7217AIPI ICM7217CIPl ICM7217IJI lCM7217BlJl TEMP. RANGE (oC) -25 to 85 -25 to 85 -25 to 85 -25 to 85 PACKAGE 28 Ld PDIP 28 Ld PDIP 28 Ld CERDIP 28 Ld CERDIP DISPLAY DRIVER TYPE Common Cathode Common Cathode Common Anode Common Anode COUNT OPTION/ MAX COUNT Decade/9999 Timing/5959 Decade/9999 Timing/5959 PKG. NO. E28.6 E28.6 F28.6 F28.6
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | Intersil and Design is a trademark of Intersil Americas Inc. | Copyright (c) Intersil Americas Inc. 2001
File Number
3167.3
1
ICM7217 Pinouts
ICM7217 (CERDIP) COMMON ANODE TOP VIEW
CARRY/BORROW 1 ZERO 2 EQUAL 3 BCD I/O 8s 4 BCD I/O 4s 5 BCD I/O 2s 6 BCD I/O 1s 7 COUNT INPUT 8 STORE 9 UP/DOWN 10 LOAD REGISTER/OFF 11 LOAD COUNTER/I/O OFF 12 SCAN 13 RESET 14 ICM7217 ICM7217B 28 D1 27 D2 26 D3 25 D4 24 VDD 23 DISPLAY CONT. 22 SEG g 21 SEG b 20 VSS 19 SEG e 18 SEG f 17 SEG d 16 SEG a 15 SEG c
ICM7217 (PDIP) COMMON CATHODE TOP VIEW
CARRY/BORROW 1 ZERO 2 EQUAL 3 BCD I/O 8s 4 BCD I/O 4s 5 BCD I/O 2s 6 BCD I/O 1s 7 COUNT INPUT 8 STORE 9 UP/DOWN 10 LOAD REGISTER/OFF 11 LOAD COUNTER/I/O OFF 12 SCAN 13 RESET 14 ICM7217A ICM7217C 28 SEG d 27 SEG b 26 SEG f 25 SEG c 24 VDD 23 SEG a 22 SEG e 21 SEG g 20 DISPLAY CONT. 19 VSS 18 D1 17 D2 16 D3 15 D4
Functional Block Diagram
ZERO 4 T.G. 4 D1 10 ZERO UP/DN COUNT U/D CL CARRY 1 1 4 T.G. 4 D2 10 ZERO U/D CL CARRY 2 2 4 T.G. 4 D3 10 ZERO U/D CL CARRY 3 3 4 T.G. 4 D4 10 ZERO U/D CL CARRY 4 4 4 4 4 4 T.G. 4 D1 REG. 4 COMP. 4 VSS 3 3 4 T.G. 4 D2 REG. 4 COMP. 4 2 2 4 T.G. 4 D3 REG. 4 COMP. 4 1 1 4 T.G. 4 D4 REG. 4 COMP. 4
VDD
RS
RS
RS
RS
CARRY/BARROW
EQUAL
8s 4s 2s 1s BDC I/O
T.G. 4 LATCH MUX 4
T.G. 4 LATCH MUX 4
T.G. 4 LATCH MUX 4
T.G. 4 LATCH MUX 4 L.C. RESET MUX. I/O AND DISPLAY CONTROL LOGIC L.R.
VDD VDD VDD
STORE RESET
VSS COUNTER VDD VSS REGISTER VDD VSS DISPLAY
CONTROL LOAD
LOAD
SEGMENT DECODER
DISPLAY BLANK + OFF 4 4 MUX. OSCILLATOR
DIGIT MUX
SEGMENT DRIVERS (7)
DIGIT DRIVERS (4)
BCD I/O INPUTS COM. ANODE: PULL DOWN COM. CATHODE: PULL UP
SCAN
A
B
C
D
E
F
G
D4
D3
D2
D1
2
ICM7217
Absolute Maximum Ratings
Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Input Voltage (Any Terminal) . . . . . . . . (VSS - 0.3V) to (VDD + 0.3V) (Note 1)
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 55 14 PDIP Package . . . . . . . . . . . . . . . . . . . 55 N/A Maximum Junction Temperature PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than VDD or less than VSS may cause destructive device latchup. For this reason it is recommended that the power supply to the device be established before any inputs are applied and that in multiple systems the supply to the ICM7217 be turned on first. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Supply Current (Lowest Power Mode), IDD (7217) Supply Current, OPERATING, IOP Supply Current, OPERATING, IOP VSUPPLY , VDD Digit Driver Output Current, IDIG SEGment Driver Output Current, ISEG Digit Driver, Output Current, IDIG SEGment Driver Output Current, ISEG ST, RS, UP/DN Input Pullup Current, IP 3 Level Input Impendance, ZIN BCD I/O Input, High Voltage VBIH BCD I/O Input, Low Voltage VBIL BCD I/O Input, Pullup Current IBPU BCD I/O Input Pulldown Current, IBPD BCD I/O, ZERO, EQUAL Outputs Output High Voltage, VOH BCD I/O, CARRY/BORROW ZERO, EQUAL Outputs Output Low Voltage, VOL Count Input Frequency, fIN Count Input Threshold, VTH Count Input Hysteresis, VHYS Count Input LO, VCIL Count Input HI, VCIH
VDD = 5V, VSS = 0V, TA = 25oC, Display Diode Drop 1 .7V, Unless Otherwise Specified TEST CONDITIONS Display Off, LC, DC, UP/DN, ST, RS, BCD I/O Floating or at VDD (Note 1) Common Anode, Display On, all "8's" Common Cathode, Display On, all "8's" Common Anode, VOUT = VDD - 2.0V Common Anode, VOUT = +1.5V Common Cathode, VOUT = +1.0V Common Cathode VOUT = VDD - 2V VIN = VDD - 2V (Note 1) MIN 140 50 4.5 140 20 -50 -9 5 40 ICM7217 Common Anode (Note 2) ICM7217 Common Cathode (Note 2) ICM7217 Common Anode (Note 2) ICM7217 Common Cathode (Note 2) ICM7217 Common Cathode VIN = VDD - 2V (Note 2) ICM7217 Common Anode VIN = +2V (Note 2) IOH = -100A IOL = 1.6mA 1.5 4.40 5 5 3.5 TYP 350 200 100 5 200 35 -75 -12.5 25 25 25 MAX 500 5.5 350 0.60 3.2V 0.4 UNIT A mA mA V mAPEAK mAPEAK mAPEAK mAPEAK A k V V V V A A V V
-20oC to 70oC Guaranteed (Note 3) (Note 3)
0 3.5
5 2 0.5 -
2 0.40 -
MHz MHz V V V V
3
ICM7217
Electrical Specifications
PARAMETER Display Scan Oscillator Frequency, fDS VDD = 5V, VSS = 0V, TA = 25oC, Display Diode Drop 1 .7V, Unless Otherwise Specified TEST CONDITIONS Free-running (SCAN Terminal Open Circuit) MIN TYP 2.5 MAX 10 UNIT kHz
Switching Specifications VDD = 5V, VSS = 0V, TA = 25oC
PARAMETER UP/DOWN Setup Time, tUCS UP/DOWN Hold Time, tUCH COUNT Pulse Width High, tCWH COUNT Pulse Width Low, tCWI COUNT to CARRY/BORROW Delay, tCB CARRY/BORROW Pulse Width tBW COUNT to EQUAL Delay, tCE COUNT to ZERO Delay, tCZ RESET Pulse Width, tRST NOTES: 1. In the ICM7217 the UP/DOWN, STORE, RESET and the BCD I/O as inputs have pullup or pulldown devices which consume power when connected to the opposite supply. Under these conditions, with the display off, the device will consume typically 750A. 2. These voltages are adjusted to allow the use of thumbwheel switches for the ICM7217. Note that a high level is taken as an input logic zero for ICM7217 common-cathode versions. 3. Parameters not tested (Guaranteed by Design). MIN 300 1500 250 250 1000 TYP 750 100 100 750 100 500 300 500 MAX UNIT ns ns ns ns ns ns ns ns ns
4
ICM7217 Timing Waveforms
SCAN 10s TYP FREE-RUNNING INTERNAL OSC OUTPUT 400s TYP FREE-RUNNING
D4 D3 D2 D1
INTERNAL (BCD AND SEGMENT ENABLE)
D4 INTERNAL (COMMON ANODE DIGIT STROBES) D3 D2 D1 INTERDIGIT BLANK
FIGURE 1. MULTIPLEX TIMING
tUCS UP/DOWN tCWH COUNT INPUT tCB CARRY/BORROW tCEL EQUAL tCZL ZERO tCZH tCEH tBW tCWL tUCH
FIGURE 2. COUNT AND OUTPUTS TIMING
5
ICM7217 Timing Waveforms
LOAD COUNTER (OR LOAD REGISTER) SCAN D4 D3 D2 D1 INTERNAL OPERATING MODE INPUT OUTPUT COUNT INHIBITED IF LOAD COUNTER
BCD I/O
DN OUT
D4 IN
D3 IN
D2 IN
D1 IN
D4 OUT
D3 OUT
= HIGH IMPEDANCE = THREE-STATE W/PULLDOWN
FIGURE 3. BCD I/O AND LOADING TIMING
Typical Performance Curves
300 4.5 VDD 6V ICM7217 ICM7217B 80 TA = 25oC V+ = 5.5V 60 ICM7217 ICM7217B
200 IDIG (mA)
ISEG (mA)
40 V+ = 4.5V V+ = 5V 20
100 25oC 85oC -20oC
0 0 1 VDD - VOUT (V) 2 3
0
0
1 VOUT (V)
2
3
FIGURE 4. TYPICAL IDIG vs V+
FIGURE 5. TYPICAL ISEG vs VOUT
6
ICM7217 Typical Performance Curves
80 V+ = 5V -20oC 60 ICM7217 ICM7217B IDIGIT (mA) 150 ICM7217A ICM7217C 200 V+ = 5V -20oC
ISEG (mA)
40 25oC 20
100
25oC
85oC
50
85oC
0
0 0 1 VOUT (V) 2 3 0 1 VOUT (V) 2 3
FIGURE 6. TYPICAL ISEG vs VOUT
FIGURE 7. TYPICAL IDIGIT vs VOUT
200 TA = 25oC 150 V+ = 5.5V ICM7217A ICM7217C 100 V+ = 4.5V
30 4.5 VDD - VSS 6V 25oC 20 ISEG (mA) ICM7217A ICM7217C
-20oC
IDIGIT (mA)
85oC 10
V+ = 5V 50
0
0
1 VOUT (V)
2
3
0
0
1
VDD - VOUT (V)
2
3
FIGURE 8. TYPICAL IDIGIT vs VOUT
FIGURE 9. TYPICAL ISEG vs VDD - VOUT
Detailed Description
Control Outputs The CARRY/BORROW output is a positive going pulse occurring typically 500ns after the positive going edge of the COUNT INPUT. It occurs when the counter is clocked from 9999 to 0000 when counting up and from 0000 to 9999 when counting down. This output allows direct cascading of counters. The CARRY/BORROW output is not valid during load counter and reset operation. When the count is 6000 or higher, a reset generates a CARRY/BORROW pulse. The EQUAL output assumes a negative level when the contents of the counter and register are equal. The ZERO output assumes a negative level when the content of the counter is 0000. The CARRY/BORROW, EQUAL and ZERO outputs will drive a single TTL load over the full range of supply voltage and ambient temperature; for a logic zero, these outputs will sink 1.6mA at 0.4V and for a logic one, the outputs will source >60A. A 10k pull-up resistor to VDD on the EQUAL or ZERO outputs is recommended for highest speed operation, and on the CARRY/BORROW output when it is being used for cascading. Figure 2 shows control outputs timing diagram. Display Outputs and Control The Digit and SEGment drivers provide a decoded 7-segment display system, capable of directly driving common anode LED displays at typical peak currents of 35mA/seg. This corresponds to average currents of 8mA/seg at 25% multiplex duty cycle. For the common cathode versions, peak segment currents are 12.5mA, corre-
7
ICM7217
sponding to average segment currents of 3.1mA. Figure 1 shows the multiplex timing. The DISPLAY pin controls the display output using three level logic. The pin is self-biased to a voltage approximately 1/2 (VDD); this corresponds to normal operation. When this pin is connected to VDD , the segments are disabled and when connected to VSS , the leading zero blanking feature is inhibited. For normal operation (display on with leading zero blanking) the pin should be left open. The display may be controlled with a 3 position SPDT switch; see Test Circuit. Multiplex SCAN Oscillator The on-board multiplex scan oscillator has a nominal freerunning frequency of 2.5kHz. This may be reduced by the addition of a single capacitor between the SCAN pin and the positive supply. Capacitor values and corresponding nominal oscillator frequencies, digit repetition rates, and loading times are shown in Table 1.
SCAN INPUT ICM7217 R1 10k R2 20k 500
SCAN INPUT ICM7217
C 1M 1M 0.01F
500
0.01F
FIGURE 10A.
FIGURE 10B.
VDD = 5V
10k
7
8
4
3k
ICM7555 3 200 2 6 0.05F SCAN INPUT ICM7217 1 8s 0.05F 0V
FIGURE 10C. FIGURE 10. BRIGHTNESS CONTROL CIRCUITS TABLE 1. ICM7217 MULTIPLEXED RATE CONTROL NOMINAL OSCILLATOR FREQUENCY 2.5kHz 1.25kHz 600Hz DIGIT REPETITION RATE 625Hz 300Hz 150Hz SCAN CYCLE TIME (4 DIGITS) 1.6ms 3.2ms 8ms
SCAN CAPACITOR None 20pF 90pF
The internal oscillator output has a duty cycle of approximately 25:1, providing a short pulse occurring at the oscillator frequency. This pulse clocks the four-state counter which provides the four multiplex phases. The short pulse width is used to delay the digit driver outputs, thereby providing inter-digit blanking which prevents ghosting. The digits are scanned from MSD (D4) to LSD (D1). See Figure 1 for the display digit multiplex timing.
During load counter and load register operations, the multiplex oscillator is disconnected from the SCAN input and is allowed to free-run. In all other conditions, the oscillator may be directly overdriven to about 20kHz, however the external oscillator signal should have the same duty cycle as the internal signal, since the digits are blanked during the time the external signal is at a positive level (see Figure 1). To insure proper leading zero blanking, the interdigit blanking time should not be less than about 2s. Overdriving the oscillator at less than 200Hz may cause display flickering. The display brightness may be altered by varying the duty cycle. Figure 10 shows several variable-duty-cycle oscillators suitable for brightness control at the ICM7217 SCAN input. The inverters should be CMOS CD4000 series and the diodes may be any inexpensive device such as lN914. Counting Control, STORE, RESET As shown in Figure 2, the counter is incremented by the
8
ICM7217
rising edge of the COUNT INPUT signal when UP/DOWN is high. It is decremented when UP/DOWN is low. A Schmitt trigger on the COUNT INPUT provides hysteresis to prevent double triggering on slow rising edges and permits operation in noisy environments. The COUNT INPUT is inhibited during reset and load counter operations. The STORE pin controls the internal latches and consequently the signals appearing at the 7-Segment and BCD outputs. Bringing the STORE pin low transfers the contents of the counter into the latches. The counter is asynchronously reset to 0000 by bringing the RESET pin low. The circuit performs the reset operation by forcing the BCD input lines to zero, and "presetting" all four decades of counter in parallel. This affects register loading; if LOAD REGISTER is activated when the RESET input is low, the register will also be set to zero. The STORE, RESET and UP/DOWN pins are provided with pullup resistors of approximately 75k. BCD I/O Pins The BCD I/O port provides a means of transferring data to and from the device. The ICM7217 versions can multiplex data into the counter or register via thumbwheel switches, depending on inputs to the LOAD COUNTER or LOAD REGISTER pins; (see below). When functioning as outputs, the BCD I/O pins will drive one standard TTL load. Common anode versions have internal pull down resistors and common cathode versions have internal pull up resistors on the four BCD I/O lines when used as inputs. LOADing the COUNTER and REGISTER The BCD I/O pins, the LOAD COUNTER (LC), and LOAD REGISTER (LR) pins combine to provide presetting and compare functions. LC and LR are 3-level inputs, being selfbiased at approximately 1/2VDD for normal operation. With both LC and LR open, the BCD I/O pins provide a multiplexed BCD output of the latch contents, scanned from MSD to LSD by the display multiplex. When either the LOAD COUNTER (Pin 12) or LOAD REGISTER (Pin 11) is taken low, the drivers are turned off and the BCD pins become high-impedance inputs. When LC
CD4069 1N4148
is connected to VDD , the count input is inhibited and the levels at the BCD pins are multiplexed into the counter. When LR is connected to VDD , the levels at the BCD pins are multiplexed into the register without disturbing the counter. When both are connected to VDD , the count is inhibited and both register and counter will be loaded. The LOAD COUNTER and LOAD REGISTER inputs are edge-triggered, and pulsing them high for 500ns at room temperature will initiate a full sequence of data entry cycle operations (see Figure 3). When the circuit recognizes that either or both of the LC or LR pins input is high, the multiplex oscillator and counter are reset (to D4). The internal oscillator is then disconnected from the SCAN pin and the preset circuitry is enabled. The oscillator starts and runs with a frequency determined by its internal capacitor, (which may vary from chip to chip). When the chip finishes a full 4-digit multiplex cycle (loading each digit from D4 to D3 to D2 to D1 in turn), it again samples the LOAD REGISTER and LOAD COUNTER inputs. If either or both is still high, it repeats the load cycle, if both are floating or low, the oscillator is reconnected to the SCAN pin and the chip returns to normal operation. Total load time is digit "on" time multiplied by 4. lf the Digit outputs are used to strobe the BCD data into the BCD I/O inputs, the input must be synchronized to the appropriate digit (Figure 3). Input data must be valid at the trailing edge of the digit output. When LR is connected to GROUND, the oscillator is inhibited, the BCD I/O pins go to the high impedance state, and the segment and digit drivers are turned off. This allows the display to be used for other purposes and minimizes power consumption. In this display off condition, the circuit will continue to count, and the CARRY/BORROW, EQUAL, ZERO, UP/DOWN, RESET and STORE functions operate as normal. When LC is connected to ground, the BCD I/O pins are forced to the high impedance state without disturbing the counter or register. See "Control Input Definitions" (Table 2) for a list of the pins that function as three-state selfbiased inputs and their respective operations. Note that the ICM7217 and ICM7217B have been designed to drive common anode displays. The BCD inputs are high true, as are the BCD outputs.
CD4069 1N4148
INPUT
OUTPUT
INPUT
OUTPUT
INPUT High Low
OUTPUT High Disconnected
INPUT High Low
OUTPUT Disconnected High
FIGURE 11A. CMOS INVERTER
FIGURE 11B. CMOS INVERTER
CD4502B INPUT A INPUT B CD74HC03 OUTPUT INPUT A OUTPUT
INPUT B
9
ICM7217
CD4069 1N4148 CD4069 1N4148
INPUT
OUTPUT
INPUT
OUTPUT
INPUT INPUT B High High Low Low INPUT A High Low High Low
OUTPUT OUTPUT Low Disconnected Disconnected Disconnected
INPUT INPUT B High High Low Low INPUT A High Low High Low
OUTPUT OUTPUT Disconnected Disconnected High Low
FIGURE 11C. CMOS OPEN DRAIN
FIGURE 11D. CMOS THREE-STATE BUFFER
FIGURE 11. DRIVING 3-LEVEL INPUTS OF ICM7217
50k DN DIGIT LINE 50k DN DIGIT LINE DISPLAY CONTROL VDD 50k
VDD DISPLAY CONTROL ICM7217A ICM7217C
ICM7217 ICM7217B FIGURE 12B. COMMON CATHODE
FIGURE 12A. COMMON ANODE
FIGURE 12. FORCING LEADING ZERO DISPLAY
VDD
VDD
DIGIT DRIVE
2N2219 OR SIMILAR
SEGMENT DRIVE
2N2219 OR SIMILAR
ICM7217 ICM7217B
VSS VDD
ICM7217 ICM7217C
VSS VDD
SEGMENT DRIVE
2N6034 OR SIMILAR
DIGIT DRIVE
2N6034 OR SIMILAR
VSS
VSS
FIGURE 13A. COMMON ANODE DISPLAY
FIGURE 13B. COMMON CATHODE DISPLAY
FIGURE 13. DRIVING HIGH CURRENT DISPLAYS
10
ICM7217
VDD = 5V VDD = 5V
35 LCD DISPLAY 37 - 40 ICM7211 2 - 26 28 SEGMENTS AND BACKPLANE D4 D3 D2 D1 DB3 DB2 DB1 DB0 34 33 32 31 30 29 28 27 4 5 6 7 8s 4s 2s 1s DC 23 20 VDD 24
COUNT STORE UP/DN RESET
8 9 10 14
D1 D2 ICM7217 D3 IJI D4
28 27 26 25
1
2
4
8
1
2
4
8
1
2
4
8
1
2
4
8
C
C
C
C
10k - 20k
FIGURE 14. LCD DISPLAY INTERFACE (WITH THUMBWHEEL SWITCHES)
The lCM7217A and the ICM7217C are used to drive common cathode displays, and the BCD inputs are low true. BCD outputs are high true. Notes on Thumbwheel Switches and Multiplexing As it was mentioned, the ICM7217 is basically designed to be used with thumbwheel switches for loading the data to the device. See Figure 14 and Figure 17. The thumbwheel switches used with these circuits (both common anode and common cathode) are TRUE BCD coded; i.e. all switches open corresponds to 0000. Since the thumbwheel switches are connected in parallel, diodes must be provided to prevent crosstalk between digits. In order to maintain reasonable noise margins, these diodes should be specified with low forward voltage drops (IN914). Similarly, if the BCD outputs are to be used, resistors should be inserted in the Digit lines to avoid loading problems. Output and Input Restrictions LOAD COUNTER and LOAD REGISTER operations take 1.6ms typical (5ms maximum) after LC or LR are released. During this load period the EQUAL and ZERO outputs are not valid (see Figure 3). Since the Counter and register are compared by XOR gates, loading the counter or register can
cause erroneous glitches on the EQUAL and ZERO outputs when codes cross. LOAD COUNTER or LOAD REGISTER, and RESET input can not be activated at the same time or within a short period of each other. Operation of each input must be delayed 1.6ms typical (5ms for guaranteed proper operation) relating to the preceding one. Counter and register can be loaded together with the same value if LC and LR inputs become activated exactly at the same time. Notice the setup and hold time of UP/DOWN input when it is changing during counting operation. Violation of UP/ DOWN hold time will result in incrementing or decrementing the counter by 1000, 100 or 10 where the preceding digit is transitioning from 5 to 6 or 6 to 5. The RESET input may be susceptible to noise if its input rise time is greater than about 500s This will present no problems when this input is driven by active devices (i.e., TTL or CMOS logic) but in hardwired systems adding virtually any capacitance to the RESET input can cause trouble. A simple circuit which provides a reliable power-up reset and a fast rise time on the RESET input is shown on Figure 15.
11
ICM7217
When using the circuit as a programmable divider (/ by n with equal outputs) a short time delay (about 1s) is needed from the EQUAL output to the RESET input to establish a pulse of adequate duration. (See Figure 16). When the circuit is configured to reload the counter or register with a new value from the BCD lines (upon reaching EQUAL), loading time will be digit "on" time multiplied by four. If this load time is longer than one period of the input count, a count can be lost. Since the circuit will retain data in the register, the register need only be updated when a new value is to be entered. RESET will not clear the register.
VDD
N.O.
0.047F 10 RESET INPUT ICM7217 5k
10k
VSS
FIGURE 15. POWER ON RESET
VDD 47pF RESET
33K EQUAL
FIGURE 16. EQUAL TO RESET DELAY
Test Circuit
a
COMMON ANODE DISPLAY
c a b g e d
D4
a b f g c e d c e d
D2
a b f g c e b d
a f b
f
f g e d
D3
c
D1
g
THUMBWHEEL SWITCHES CARRY ZERO D4 BCD I/O 8s BCD I/O 4s BCD I/O 2s BCD I/O 1s COUNT INPUT D3 D2 D1 EQUAL 1 2 3 4 5 6 7 STORE UP/DOWN LOAD REGISTER LOAD COUNTER SCAN RESET VDD N.O. VDD 8 9 10 11 12 13 14 ICM7217 ICM7217B 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DISPLAY CONTROL
9999
+5V VSS
12
ICM7217 Applications
3-Level Inputs ICM7217 has three inputs with 3-level logic states; High, Low and Disconnected. These inputs are: LOAD REGISTER/OFF, LOAD COUNTER/I/O OFF and DISPLAY CONT. The circuits illustrated on Figure 11 can be used to drive these inputs in different applications. Fixed Decimal Point In the common anode versions, a fixed decimal point may be activated by connecting the DP segment lead from the appropriate digit (with separate digit displays) through a 39 series resistor to Ground. With common cathode devices, the DP segment lead should be connected through a 75 series resistor to VDD . To force the device to display leading zeroes after a fixed decimal point, use a bipolar transistor and base resistor in a configuration like that shown in Figure 12 with the resistor connected to the digit output driving the DP for left hand DP displays, and to the next least significant digit output for right hand DP display. Driving Larger Displays For displays requiring more current than the ICM7217 can provide, the circuits of Figure 13 can be used. LCD Display Interface The low-power operation of the ICM7217 makes an LCD interface desirable. The Intersil ICM7211 4-digit, BCD-to-LCD display driver easily interfaces to the ICM7217 as shown in Figure 14. Total system power consumption is less than 5mW. System timing margins can be improved by using capacitance to ground to slow down the BCD lines. The 10k - 20k resistors on the switch BCD lines serve to isolate the switches during BCD output. Unit Counter with BCD Output The simplest application of the ICM7217 is a 4-digit unit counter (Figure 18). All that is required is an ICM7217, a power supply and a 4 digit display. Add a momentary switch for reset, an SPDT center-off switch to blank the display or view leading zeroes, and one more SPDT switch for up/ down control. Using an ICM7217A with a common-cathode calculator-type display results in the least expensive digital counter/display system available. Inexpensive Frequency Counter/ Tachometer This circuit uses the low power ICM7555 (CMOS 555) to generate the gating, STORE and RESET signals as shown in Figure 19. To provide the gating signal, the timer is configured as an a stable multivibrator, using RA, RB and C to provide an output that is positive for approximately one second and negative for approximately 300s - 500s. The positive waveform time is given by tWP = 0.693 (RA + RB)C while the negative waveform is given by two = 0.693 RBC. The system is calibrated by using a 5M potentiometer for RA as a "coarse" control and a 1k potentiometer for RB as a "fine" control. CD40106Bs are used as a monostable multivibrator and reset time delay. Tape Recorder Position Indicator/controller The circuit in Figure 20 shows an application which uses the up/down counting feature of the ICM7217 to keep track of tape position. This circuit is representative of the many applications of up/down counting in monitoring dimensional position. In the tape recorder application, the LOAD REGISTER, EQUAL and ZERO outputs are used to control the recorder. To make the recorder stop at a particular point on the tape, the register can be set with the stop point and the EQUAL output used to stop the recorder either on fast forward, play or rewind. To make the recorder stop before the tape comes free of the reel on rewind, a leader should be used. Resetting the counter at the starting point of the tape, a few feet from the end of the leader, allows the ZERO output to be used to stop the recorder on rewind, leaving the leader on the reel. The 1M resistor and 0.0047F capacitor on the COUNT INPUT provide a time constant of about 5ms to debounce the reel switch. The Schmitt trigger on the COUNT INPUT of the ICM7217 squares up the signal before applying it to the counter. This technique may be used to debounce switch-closure inputs in other applications. Precision Elapsed Time/Countdown Timer The circuit in Figure 21 uses an ICM7213 precision one minute/one second timebase generator using a 4.1943MHz crystal for generating pulses counted by an ICM7217B. The thumbwheel switches allow a starting time to be entered into the counter for a preset-countdown type timer, and allow the register to be set for compare functions. For instance, to make a 24-hour clock with BCD output the register can be preset with 2400 and the EQUAL output used to reset the counter. Note the 10K resistor connected between the LOAD COUNTER terminal and Ground. This resistor pulls the LOAD COUNTER input low when not loading, thereby inhibiting the BCD output drivers. This resistor should be eliminated and SW4 replaced with an SPDT center-off switch if the BCD outputs are to be used. This technique may be used on any 3-level input. The 100k pullup resistor on the count input is used to ensure proper logic voltage swing from the ICM7213. For a less expensive (and less accurate) timebase, an ICM7555 timer may be used in a configuration like that shown in Figure 19 to generate a 1Hz reference. 8-Digit Up/Down Counter This circuit (Figure 22) shows how to cascade counters and retain correct leading zero blanking. The NAND gate detects whether a digit is active since one of the two segments a or b is active on any unblanked number. The flip flop is clocked by the least significant digit of the high order counter, and if this digit is not blanked, the Q output of the flip flop goes high and turns on the NPN transistor, thereby inhibiting leading zero blanking on the low order counter.
13
ICM7217
It is possible to use separate thumbwheel switches for presetting, but since the devices load data with the oscillator free-running, the multiplexing of the two devices is difficult to synchronize. Precision Frequency Counter/Tachometer The circuit shown in Figure 23 is a simple implementation of a four digit frequency counter, using an ICM7207A to provide the one second gating window and the STORE and RESET signals. In this configuration, the display reads hertz directly. With Pin 11 of the ICM7027A connected to VDD , the gating time will be 0.1s; this will display tens of hertz at the least significant digit. For shorter gating times, an ICM7207 may be used (with a 6.5536MHz crystal), giving a 0.01s gating with Pin 11 connected to VDD , and a 0.1s gating with Pin 11 open. To implement a four digit tachometer, the ICM7207A with one second gating should be used. To get the display to read directly in RPM, the rotational frequency of the object to be measured must be multiplied by 60. This can be done electronically using a phase-locked loop, or mechanically by using a disc rotating with the object with the appropriate number of holes drilled around its edge to interrupt the light from an LED to a photo-dector. For faster updating, use 0.1s gating, and multiply the rotational frequency by 600. Auto-Tare System This circuit uses the count-up and count-down functions of the ICM7217, controlled via the EQUAL and ZERO outputs, to count in SYNC with an ICL7109A and ICL7109D Converter as shown in Figure 24. By RESETing the ICM7217 on a "tare" value conversion, and STORE-ing the result of a true value conversion, an automatic fare subtraction occurs in the result. The ICM7217 stays in step with the ICL7109 by counting up and down between 0 and 4095, for 8192 total counts, the same number as the ICL7109 cycle. See applications note No. A047 for more details.
TABLE 2. CONTROL INPUT DEFINITIONS ICM7217 INPUT STORE TERMINAL 9 VOLTAGE VDD (or floating) VSS VDD (or floating) VSS VDD (or floating) VSS Unconnected VDD VSS Unconnected VDD VSS FUNCTION Output Latches Not Updated Output Latches Updated Counter Counts Up Counter Counts Down Normal Operation Counter Reset Normal Operation Counter Loaded with BCD data BCD Port Forced to Hi-Z Condition Normal Operation Register Loaded with BCD Data Display Drivers Disabled; BCD Port Forced to Hi-Z Condition, mpx Counter Reset to D4; mpx Oscillator Inhibited Normal Operation Segment Drivers Disabled Leading Zero Blanking Inhibited
UP/DOWN
10
RESET
14
LOAD COUNTER/ I/O OFF
12
LOAD REGlSTER/ OFF
11
DISPLAY CONTrol
23 Common Anode 20 Common Cathode
Unconnected VDD VSS
14
ICM7217
TO D4 STROBE C 8 1 8 TO D1 STROBE C 1 8 TO D4 STROBE C 1 8 TO D1 STROBE C 1
4
2
4
2
4
2
4
2
IN914 OR EQUIVALENT
8
4
2
1
8
4
2
1
TO BCD INPUTS OF ICM7217, ICM7217B
TO BCD INPUTS OF ICM7217A, ICM7217C
FIGURE 17. THUMBWHEEL SWITCH/DIODE CONNECTIONS
CARRY ZERO
1 2
21 - 23 25 - 28 COMMON CATHODE LED DISPLAY
7 SEGMENTS
4 BCD I/O 5 6 7 COUNT INPUT STORE 8 9 ICM7217A 24 20
DISPLAY CONTROL
VDD BLANK NORMAL INHIBIT LZB
19
14 RESET
15 - 18
4-DIGIT
FIGURE 18. UNIT COUNTER
15
ICM7217
RA 7
5M
8 VDD DIS
4 RS OUT 3
3K
10K 9 STORE VDD 24
0.047F 1K RB 2 6 TR TH VSS 0.47F C 1 CV 5 14 RESET VSS GND INVERTERS: CD40106B NANDS: CD4011B COUNT INPUT 20 GATE 8 ICM7217 COUNT
LED DISPLAY
FIGURE 19A.
300s GATE 50s STORE 1s
RESET
FIGURE 19B. FIGURE 19. INEXPENSIVE FREQUENCY COUNTER
STOP
LOGIC TO GENERATE RECORDER CONTROL SIGNALS
ZERO EQ 1 CARRY ZERO
d b f c
28
COMMON CATHODE LED DISPLAY
REEL SWITCH CLOSED ONCE/REV VDD 1M
THUMBWHEEL SWITCHES
EQUAL
7 SEGMENTS
4 DIGIT
9999
VDD FORWARD REWIND VDD N.O. N.O. SET PT
BCD I/O
VDD
a e g
BLANK NORMAL INHIBIT LZB D1 D2 D3 D4 4 DIGITS
COUNT IN STORE UP/DOWN LOAD REG LOAD CTR SCAN RESET
VDD
0.0047F
RESET
FIGURE 20. TAPE RECORDER POSITION INDICATOR
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ICM7217
VDD 100K
RUN MIN/SEC
1 2 3 30pF 4 5 6 7 ICM7213
14 13 12 11 10 9 8
STOP
SW1
RUN HRS/MIN
VDD (4V MAX)
EQUAL ZERO 4
TO LOGIC GENERATING SIGNALS FOR CONTROL OF EXTERNAL EQUIPMENT
30pF
4.1943MHz CRYSTAL RS < 75
CARRY ZERO EQUAL
D1 D2 D3 D4 4 DIGITS
THUMBWHEEL SWITCHES
5959
ELAPSED COUNTDOWN LOAD SET PT. DISPLAY OFF VDD VDD SW2 SW3 10K
4
BCD I/O
VDD DIS. CONT.
VDD
BLANK SW6 INHIBIT LZB
VDD
g
COUNT IN STORE UP/DOWN LOAD REG LOAD CTR SCAN RESET ICM7217
b
VSS
e f d a c
COMMON ANODE LED DISPLAY
7
SEGMENTS
VDD
PRESET SW4 RESET SW5
FIGURE 21. PRECISION TIMER
17
ICM7217
COMMON-ANODE LED DISPLAY
COUNT INPUT 4 DIGITS D1 BCD OUTPUTS HIGH ORDER DIGITS 24 20 ICM7217 V+ 7 SEGMENTS 4 1 4-7 25 - 28 CARRY/BORROW 4 DIGITS 7 SEGMENTS
CARRY OUT 4
1 4-7
25 - 28
BCD OUTPUTS HIGH ORDER DIGITS
8 V+ UP/DOWN N.O. RESET 9 10 14 HIGH ORDER 1A 15 - 19 21, 22 1B ICM7217
1/ 4 CD4011
24 20
V+
23 8 9 10 14 LOW ORDER 15 - 19 21, 22
V+ 50k 3k
CD4013 Q CL
1/ 2
D NPN TRANSISTOR
50k
FIGURE 22. 8-DIGIT UP/DOWN COUNTER
18
V+ = 5V 22pF 22pF 10k 4 BCD OUT 5 6 7 24 25 - 28
COMMON ANODE LED DISPLAY
4 DIGITS
14 2 13 ICM7207A 10k 4 5 6 CRYSTAL f = 5.24288MHz RS = 75
1/
ICM7217
10 COUNT STORE
4
8 9
15 - 19 21, 22
7 SEGMENTS
CD4011 RESET 14 20
INPUT
FIGURE 23. PRECISION FREQUENCY COUNTER (MHz MAXIMUM)
400mV FULL SCALE INPUT + D 0.1F 1 GND 2 STATUS 3 POL 4 OR 5 B12 6 B11 7 B10 8 B9 9 B8 10 B7 11 B6 12 B5 13 B4 14 B3 15 B2 16 B1 17 TEST 18 LBEN 19 HBEN 20 CE/LOAD ICM7109 VDD 40 REF IN - 39 REF CAP - 38 REF CAP + 37 REF IN + 36 IN HI 35 IN LO 34 COMMON 33 INT 32 AZ 31 BUF 30 REF OUT 29 VSS 28 SEND 27 RUN/HOLD 26 BUF OSC OUT 25 OSC SEL 24 OSC OUT 23 OSC IN 22 MODE 21 +5V TARE +5V 100pF 100K +5V 10F 0.1F 0.22F +5V S Q Q D S Q Q
+5V 4 DIGIT COMMON ANODE LED DISPLAY
270 7 LED MINUS SIGN
+5V 100K
R
R
1F
10K 5 x 1N4148 1 CARRY/ BORROW 2 ZERO 3 EQUAL 4 BCD 8 5 BCD 4 6 BCD 2 D0 28 D1 27 D2 26 D3 25 VDD 24 DISP. 23 CONT. G 22 B 21 VSS 20 E 19 F 18 D 17 A 16 C 15 +5V 47F 7
47K
100K
7 BCD 1 8 COUNT 9 STORE 10 UP/DOWN 11 LOAD REG. 12 LOAD CTR. 13 SCAN 14 RESET
ICM7217
FIGURE 24. AUTO-TARE SYSTEM FOR A/D CONVERTER
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ICM7217
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